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CXA2050S
Y/C/RGB/D for PAL/NTSC Color TVs
Description The CXA2050S is a bipolar IC which integrates the luminance signal processing, chroma signal processing, RGB signal processing, and sync and deflection signal processing functions for PAL/NTSC system color TVs onto a single chip. This IC includes deflection processing functions for wide-screen TVs, and is also equipped with a SECAM decoder interface, making it possible to construct a TV system that supports multiple color systems. 64 pin SDIP (Plastic)
Features * I2C bus compatible * Compatible with both PAL and NTSC systems (also compatible with SECAM if a SECAM decoder is connected) * Built-in deflection compensation circuit capable of supporting various wide modes * Countdown system eliminates need for H and V oscillator frequency adjustment * Automatic identification of 50/60Hz vertical frequency (forced control possible) * Non-interlace display support (even/odd selectable) * Automatic identification of PAL, NTSC, and SECAM color systems (forced control possible) * Automatic identification of 4.43MHz/3.58MHz crystal (forced control possible) * Non-adjusting Y/C block filter * One CV input, one set of Y/C inputs, two sets of analog RGB inputs (one set of which can serve as both analog and digital inputs) * Built-in AKB circuit * Support for forcing YS1 off Applications Color TVs (4:3, 16:9) Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25C, SGND, DGND = 0V) * Supply voltage SVCC1, 2, DVCC1, 2 -0.3 to +12 V * Operating temperature Topr -20 to +65 C * Storage temperature Tstg -65 to +150 C * Allowable power consumption PD 1.7 W * Voltages at each pin -0.3 to SVCC1, SVCC2, DVCC1, DVCC2 + 0.3 V Operating Conditions Supply voltage
SVCC1, 2 DVCC1, 2
9.0 0.5 9.0 0.5
V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E96403-PS
Block Diagram
EXT SYNC IN
VM
SYNCOUT
SDA
DCTRAN
SCL
BLHOLD
VSFIL
HSIN
CERA
VSIN
63
54 59 52 47 44
57 61
56
55 51 45
53 46
2Vp-p H SYNC SEP 32fH VCO PHASE DET V SYNC SEP GATE Sand Castle PHASE DET. 1/32 2fH H POSI AFC CD MODE PHASE SHIFT DC SHARP TRAN AGING D PIC DL SHP f0 V FREQ 50/60 ID SHARP NESS D PIC GATE Count Down 525/625 PRE/OVER TOT TOT INTERLACE PIC D-COL KILLER DET YS1 OFF INTER -LACE
AFCFIL
AFCPIN/ HOFF
L2FIL
42 DVCC1 50 DVCC2 48 DGND H.DRIVE 43 HD OUT 12 SCPOUT 36 VTIM 40 VAGCSH VPOSI, VOFF, VSIZE
6dB
VM
EXT SYNC
VIDEO OUT 58
CV/YC
SUB CONT DL DC TRAN CLP
TRAP OFF
CVIN 60
1Vp-p
YIN 62
VIDEO SW
SUB CONT
TRAP
ACC DET
SYSTEM IDENT
1Vp-p
YS2
YM
RSH
B1IN
IREF
R2IN
X358
X443
R1IN
G1IN
YOUT
YRET
G2IN
B2IN
APCFIL
ABLFIL
FSCOUT
SECAM REF
- (R-Y) OUT
- (B-Y) OUT
- (R-Y) IN
- (B-Y) IN
YS1/VM
ABLIN/ VCOMP
GSH
BSH
-2-
PAL ID DEM Y/C MIX YS1 SW YM/YS2 SW PIC DEM AXIS fsc B-Y 9 10 11 13 14 15 COL 17 18 19 20 21 22 23 24 25 7 fsc R-Y COLOR & AXIS
CIN 64
ACC
COLOR SW
41 SAWOSC VD + OUT 38 WIDE /VPROT Sawtooth Gen. 37 VD - OUT /VPROT VLIN, SCORR WIDE Parabola 39 E-WOUT Gen. BRT GB DRV GB CUT LIMIT 28 ROUT OSD MIX DCOL BRT GB DRV CUT OFF BLK 30 GOUT 32 BOUT ABL ABL 35 34 EHT H, V HV COMP 33 IKIN AKB AKB OFF 27 29 31
SUB COLOR
SVCC1
1
SVCC2 26
APC
HUE
SGND1
8
XTAL HUE
SGND2 16
IREF
VCO
49
2
4
3
6
CXA2050S
1 2 3 4 5 6 7 8
SVCC1 CIN EXT SYNC IN YIN DCTRAN CVIN BLHOLD VIDEO OUT SDA SCL VM SYNCOUT HSIN VSIN VSFIL DVCC2 IREF DGND CERA AFCFIL L2FIL B1IN YS2 YM R2IN G2IN B2IN SVCC2 RSH ROUT GSH GOUT BSH BOUT AFCPIN/HOFF HD OUT DVCC1 SAWOSC VAGCSH E-WOUT VD + OUT/VPROT VD - OUT/VPROT VTIM ABLFIL ABLIN/VCOMP IKIN APCFIL X443 X358 TEST FSC OUT SECAM REF SGND1 - (R-Y) OUT - (B-Y) OUT YOUT SCPOUT YRET - (R-Y) IN - (B-Y) IN SGND2 YS1/VM R1IN G1IN
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
-3-
CXA2050S
CXA2050S
Pin Description Pin No. 1 SVCC1 Symbol Equivalent circuit Description Power supply for Y/C block.
4.6V
2
APCFIL
2
1.2k 1.2k
CR connection for the chroma APC laglead filter.
4k
3
X443
3 500 200A
Connect a 4.433619MHz crystal oscillator.
4k
4
X358
4 500 200A
Connect a 3.579545MHz crystal oscillator.
1k
5
TEST
5 15k
Test pin. Outputs a 0 to 3V V-SYNC SEP with positive polarity. If not used, leave this pin open.
1.2k
6
FSCOUT
6 147 280A
Subcarrier output. Output level: 5.2VDC, 0.4Vp-p
-4-
CXA2050S
Pin No.
Symbol
Equivalent circuit
Description
6k
20p
7
SECAMREF
7 250A
7.2V
SECAM decoder interface. This pin serves as both a 4.43MHz output and as a SECAM identification input/output pin.
8
SGND1
--
GND for Y/C block.
200A
9 10
- (R-Y) OUT - (B-Y) OUT
9 10
Color difference signal outputs. Go to high impedance when the SECAM system is detected. Standard output levels for 75% CB: B-Y: 0.665Vp-p R-Y: 0.525Vp-p 5.7VDC when killer is ON.
500
11
YOUT
11 30k 400A
Luminance signal output. Black level is 3.5VDC. Standard output level for 100 IRE input: 1Vp-p
1k
12
SCPOUT
12 10k 1k
Sand castle pulse output. The 0 to 5V BGP pulse, the phase of which is controlled through the bus, is superimposed with the 0 to 2V H and VBLK pulse for output.
13
YRET
13 1.5k 70k
Luminance signal input. Clamped to 4.8V at the burst timing. Standard input level for 100 IRE input: 1Vp-p
-5-
CXA2050S
Pin No.
Symbol
Equivalent circuit
Description
14 15
- (R-Y) IN - (B-Y) IN
14 15 1.5k 70k
Color difference signal inputs. Clamped to 5.5V at the burst timing. Standard input levels for 75% CB: B-Y: 1.33Vp-p R-Y: 1.05Vp-p
16
SGND2
GND for the RGB block. Input which combines YS1SW control with VM circuit ON/OFF function. Supports with ternary. VMSW (VthVM = 0.9V) VILVM 0.3V VM circuit ON VIHVM 1.5V VM circuit OFF YS1SW (VthYS1 = 2.5V) VILYS1 1.7V Y/color difference input selected VIHYS1 3.3V RGB1 input selected Setting YS1OFF of I2C bus to 1, input for this pin is invalid.
100A
17
YS1/VM
17
10k 20k
200
18 19 20
R1IN G1IN B1IN
18 19 20 30k
Analog R, G and B signal inputs. Input a 0.7Vp-p (no sync, 100 IRE) signal via a capacitor. The signal is clamped to 5.7V at the burst timing of the signal input to the HSIN input (Pin 53).
100A
21
YS2
21 40k
YM/YS2SW YS2 control input. When YS2 is high, the RGB2 block signal is selected; when YS2 is low, the YS1SW output signal is selected. VILMAX = 0.4V VIHMIN = 1.0V
100A
22
YM
22 40k
YM/YS2 SW YM control input. When YM is high, the YS1SW output signal is attenuated by 6dB. VILMAX = 0.4V VIHMIN = 1.0V
-6-
CXA2050S
Pin No.
Symbol
Equivalent circuit
Description
100A 200
23 24 25
R2IN G2IN B2IN
23 24 25 30k
Analog/digital (dual-purpose) RGB signal inputs. The input signals are input via capacitors. When using analog input, input a 0.7Vp-p signal (no sync, 100 IRE); when using digital input, input a signal of at least 1.5Vp-p (Vth = 1.2V). The display level is 78 IRE. When using digital input, digital input is selected regardless of the YS2 setting. In addition, the VM output is turned off. These pins are clamped to 5.7V at the burst timing of the signal input to the HSIN input (Pin 53).
26
SVCC2
Power supply for RGB block.
200
27 29 31
RSH GSH BSH
27 29 31
Sample-and-hold for R, G and B AKB. Connect to GND via a capacitor. When not using AKB (manual CUTOFF mode), R, G and B cut-off voltage can be controlled by applying a control voltage to each pin. The control voltage is 4.5 1V.
200
28 30 32
ROUT GOUT BOUT
28 30 32 12k 1.1mA
R, G and B signal outputs. 2.5Vp-p is output during 100% white input.
1k
33
IKIN
33 50A
Input the signal converted from the CRT beam current (cathode current Ik) to a voltage via a capacitor. The V blanking part is clamped to 2.7V at the V retrace timing. The input for this pin is the reference pulse return, and the loop operates so that the Rch is 1Vp-p and the G and Bch are 0.81Vp-p. The G and Bch can be varied by 0.5V by the bus CUTOFF control. When not using AKB, this pin should be open.
-7-
CXA2050S
Pin No.
Symbol
Equivalent circuit
Description
1.5V
34
ABLIN/VCOMP
34 147
ABL control signal input and VSAW high voltage fluctuation compensation signal input. High voltage compensation has linear control characteristics for the pin voltage range of about 8V to 1V. The control characteristics can be varied through EHT-V control of the bus. ABL begins to have effect below a threshold voltage of about 1.2V. ABL functions as average value type.
100k
35
ABLFIL
35 1.2k
Connect a capacitor to form the LPF of the ABL control signal.
1k
36
VTIM
36 10k 1k
V timing pulse output. Outputs the timing pulse from V sync identification to the end of V blanking. Pulses are positive polarity from 1 to 6V. During zoom mode, the V blanking pulse which has been expanded before and after the V sync is superimposed and output as the 1 to 3V pulse.
700
37
VD - OUT/VPROT
37
30k 400A 24k
V sawtooth wave output and V protect signal input. When a large current (3mA) is drawn from this pin, the RGB outputs are all blanked and "1" is output to the status register VNG.
700
38
VD + OUT/VPROT
38
30k 24k 400A
Serves as both a V sawtooth wave output with the reverse polarity of VD - OUT, and a Vprotect signal input. The Vprotect function can even be applied to this pin.
-8-
CXA2050S
Pin No.
Symbol
Equivalent circuit
Description
1.4k
39
E-WOUT
39
15k 78k 800A
V parabola wave output.
40
VAGCSH
40 1.2k
Sample-and-hold for AGC which maintains the V sawtooth wave at a constant amplitude. Connect to GND via a capacitor.
41
SAWOSC
300 41 100
Connect a capacitor to generate the V sawtooth wave. For the capacitor, use an MPS (metalized polyester capacitor), etc., with a small tan .
42
DVCC1
Power supply for the V deflection block.
43
HD OUT
43 147 20k
H drive signal output. This signal is output with the open collector.
147 10k
44
AFCPIN/HOFF
44 10k 68k 4.2V
H deflection pulse input for H AFC. Input an about 5Vp-p pulse via a capacitor. Set the pulse width to 10 to 12s. This pin is also used as the holddown signal input for the HD output, and if this pin is 1V or less for a 7V cycle or longer, the hold-down function operates and the HD output is held to 9VDC. In addition, the RGB outputs are all blanked. Outputs "1" to the status register XRAY.
-9-
CXA2050S
Pin No.
Symbol
Equivalent circuit
Description
45
L2FIL
45 100
Filter for H AFC. Connect to GND via a capacitor. The H phase can also be controlled from this pin by leading current in and out of this capacitor. As the pin voltage rises, the picture shifts to the left; as the pin voltage drops, the picture shifts to the right.
46
AFCFIL
1.2k 46 46k
CR connection for the AFC lag-lead filter.
10k
47
CERA
47 400A
Connect the 32 x FH VCO ceramic oscillator.
48
DGND
GND for the deflection block.
49
IREF
147 49
20k
Internal reference current setting. Connect to GND via a resistor with an error of less than 1% (such as a metal film resistor).
50
DVCC2
Power supply for the H deflection block.
1k
51
VSFIL
51
Filter for V sync separation. Connect to GND via a capacitor.
- 10 -
CXA2050S
Pin No.
Symbol
Equivalent circuit
Description
15k 147 52 4.1V 20A
52
VSIN
Sync signal input for V sync separation. Input a 2Vp-p Y signal (or a 0.6Vp-p sync signal).
14k 147 53 3.2V 10A
53
HSIN
Sync signal input for H sync separation. Input a 2Vp-p Y signal (or a 0.6Vp-p sync signal).
1.2k
54
SYNCOUT
54
147
40k 240A
Sync signal output for VSIN and HSIN. The output can be selected from the internal sync signals (Pin 60 or Pin 62) or the external sync signal (Pin 63) by the I2C bus. Output signal level: 2Vp-p (0.6Vp-p sync only) Input/output gain: 6dB Outputs the differential waveform of the VM (Velocity Modulation) Y signal. The signal advanced for 200ns from YOUT is output. The delay time versus YIN is determined by the DL setting of the I2C bus. This output level can be set at 2.65Vp-p or 1.1Vp-p by the I2C bus. Pedestal level is DC6.2V. This output can also be turned off by YS1, YM, and YS2.
500 1.2k
55
VM
55
147 400A
30k
4k 56
56
SCL
I2C bus protocol SCL (Serial Clock) input. VILMAX = 1.5V VIHMIN = 3.5V
- 11 -
CXA2050S
Pin No.
Symbol
Equivalent circuit
Description
4k 57
57
SDA
I2C bus protocol SDA (Serial Data) I/O. VILMAX = 1.5V VIHMIN = 3.5V VOLMAX = 0.4V
1.2k
58
VIDEO OUT
58 147 200A
The input signal from CVIN pin and YIN pin is selected by I2C bus, and output externally.
9A 4.6V
59
BLHOLD
4k 59 20k
20k 1.2k
Capacitor connection for black peak hold of the dynamic picture (black expansion).
4.6V
60
CVIN
60 1A
Composite video signal input. Input the 1Vp-p (100% white including sync) CV signal via a capacitor. The sync level of the input signal is clamped to 3.8V. In addition, this pin detects input video signal HSYNC, and outputs the status via the status register CVSYNC.
2V
61
DCTRAN
61
4k 2k
1.2k
Connect a capacitor that determines the DC transmission ratio to GND.
- 12 -
CXA2050S
Pin No.
Symbol
Equivalent circuit
Description
4.6V
62
YIN
62 1A
Y signal input. Input a 1Vp-p (100% white including sync) Y signal via a capacitor. The sync level of the input signal is clamped to 3.8V.
4.6V
63
EXT SYNC IN
63 1A
External sync signal input. Input a 0.3Vp-p sync signal (or a 1Vp-p CV signal or Y signal) via a capacitor. The sync level of the input signal is clamped to 3.8V.
30k
64
CIN
64 50k
5.2V
Chroma signal input. Input a C signal with a burst level of 300mVp-p via a capacitor. Input signal is biased to 4.5V internally.
- 13 -
Electrical Characteristics Setting conditions * Ta = 25C, SVCC1, 2 = DVCC1, 2 = 9V, SGND1, 2 = DGND = 0V * Measures the following after setting the I2C bus register as shown in "I2C Bus Register Initial Settings".
Measurement conditions Measurement pins 1, 26 Measure the pin inflow current. 40 67 49 30 Measure the pin inflow current. 42, 50 90 65 Measurement contents Min. Typ. Max. VCC = 9.0V, Bus data = center VCC = 9.0V, Bus data = center Unit mA mA
No.
Item
Symbol
1
Signal block current consumption
SICC
2
Sync block current consumption
DICC
Sync deflection block items AFC MODE = 0h HDRIVE output frequency 43 15.55 15.734 15.90 kHz
3
Horizontal free-running frequency
fHFR
4 SYNCIN: composite sync
Horizontal sync pull-in range --
fHR
Confirm that I2C status register HLOCK is 1 (the pull-in range when fH is shifted from 15.734kHz).
Measure the pulse width for the section where the HDRIVE output is high.
-400
--
400
Hz
- 14 -
SYNCIN: composite sync 43 12
VBGPh
5
HD output pulse width
HDw
24.5
25.5
26.5
s
6
SCP BLK output pulse width
VBLKh
SCP Measure the pulse width for the section where the BLK output is high. SCP Measure the pulse width for the section where the BGP output is high. 12
11.6
12.1
12.6
s
VBLKh
7
SCP BGP output pulse width
VBGPh
3.35 Measure the VDRIVE output Vp-p.
3.75
4.15
s
8
VDRIVE output amplitude
VSp-p
37, 38
VSp-p
0.9
1.0
1.1
V
SYNCIN: composite sync
46: VSIN in
9
VDRIVE output center potential
VSdc
37, 38
VDRIVE+ 10.79ms VSdc
2.9
3.0
3.1
V
CXA2050S
No. Unit Measure the EWDRIVE output Vp-p. 39
VEWp-p
Item
Symbol
Measurement conditions Measurement pins Measurement contents Min. Typ. Max.
10 0.42 0.52 0.62
EWDRIVE output amplitude
VEWp-p
V
SYNCIN: composite sync
46: VSIN in
11 39
VEW dc 10.79ms
EWDRIVE output center potential 3.8
VEWdc
3.95
4.1
V
Signal block items
12 28, 30, 32
R, G and B output amplitude
CVIN: 0.7Vp-p /100 IRE
VRout1
Output amplitude when a video signal with an amplitude of 0.7Vp-p/100 IRE is input.
2.25
2.5
2.85
V
- 15 -
V1 CVIN: 100 IRE 50 IRE V2
13 28, 30, 32
R, G and B output linearity
Lin
Lin =
V1 x 100 V2 x 2
96
100
104
%
CVIN: fsc, 50 IRE
14 TRAPOFF = 0/1 TRAP-F0 = 7h
C-TRAP attenuation
C-Trap3.58
28
(3.58MHz)
Input fsc to CVIN. Ratio of the fsc component of the Yout amplitude when CTRAP = 1 against the Yout amplitude when CTRAP = 0.
f = 3.58MHz
--
-38
--
dB
CXA2050S
No. Unit
Item
Symbol
Measurement conditions Measurement pins Measurement contents Min. Typ. Max.
CVIN: fsc, 50 IRE
15 28 -- -31 -- TRAPOFF = 0/1 TRAP-F0 = 7h
f = 4.43MHz
C-TRAP attenuation (4.43MHz)
C-Trap4.43
Input fsc to CVIN. Ratio of the fsc component of the Yout amplitude when CTRAP = 1 against the Yout amplitude when CTRAP = 0. dB
50 IRE f = 3MHz
16 55
Vvm
VM output
Vvm
CVIN: 3MHz, 50 IRE VM = 1 1.95
2.3
2.65
V
17 9
Color difference -(R-Y) output
CIN 450mVp-p fsc + 0, fsc + 180 - (B-Y) OUT
Vr-y
4.43MHz PAL input burst fsc 300mVp-p 640mVp-p fsc + 90
- (R-Y) OUT Vr-y
440
510
570
mV
- 16 -
10 SUB-COLOR = 7h
ROUT - (R-Y) IN: 525mVp-p
18
Color difference -(B-Y) output
Vb-y
570
Vb-y
640
710
mV
19 PAL input: COLOR = 1Fh
Color gain -(R-Y)
Vcolr-y
28
Vcolr-y
1.1
1.3
1.5
V
20 PAL input: COLOR = 1Fh
Color gain -(B-Y)
- (B-Y) IN: 665mVp-p
BOUT
Vcolb-y
30
Vcolb-y
1.4
1.6
1.8
V
CXA2050S
No. Measurement pins Unit deg dB Hz -- -- -- ROUT, BOUT 28
CVIN: 100IRE Vp-p
Item Measurement contents -9 -- Confirm that the burst frequency is pulled in at 3.58MHz 400Hz. -400 -- 400 -37 -- 0 9 Min. Typ. Max. HUE = 1Fh, SUB - HUE = 7h CVIN: Burst only
Symbol
Measurement conditions
21
Hue center offset
offset
22
Killer point
KP
23
APC pull-in range
fAPC
24
Dynamic color operation R output 94
GdcolR
96
98
%
25
Dynamic color operation B output D-COL = 0/1 30 GdcolR =
GdcolB
Vp-p (DCOL = 1) x 100 Vp-p (DCOL = 0) Vp-p (DCOL = 1) GdcolB = x 100 Vp-p (DCOL = 0) Output amplitude ratio when the R, G and BOUT YM = 1 and 0
102
104
106
%
- 17 -
28, 30, 32 YS1: 5V RGB1IN: 0.7Vp-p 28
RGB1 IN
26
YM gain
GYM
-7.1
-6.1
-5.1
dB
27
R output amplitude during linear R1 input
VLR1out
VLR1out = Vout
1.85
2.05
2.25
V
28
G output amplitude during linear G1 input YS1: 5V RGB1IN: 0.7Vp-p
VLG1out
30
R, G, B out
VLG1out = Vout
1.85
2.05
2.25
V
29
B output amplitude during linear B1 input YS1: 5V RGB1IN: 0.7Vp-p
VLB1out
32
VLB1out = Vout
1.85
2.05
2.25
V
CXA2050S
No. Measurement pins Unit Measurement contents Min. Typ. Max.
Item
Symbol
Measurement conditions
30 28 VLR2out = Vout 1.85
R output amplitude during linear R2 input
YS2: 1V RGB2IN: 0.7Vp-p
RGB2 IN
VLR2out
2.05
2.25
V
31 30 VLG2out = Vout
R, G, B out
G output amplitude during linear G2 input
YS2: 1V RGB2IN: 0.7Vp-p 1.85 2.05
VLG2out
2.25
V
32 32
B output amplitude during linear B2 input
YS2: 1V RGB2IN: 0.7Vp-p VLB2out = Vout
VLB2out
1.85
2.05
2.25
V
- 18 -
RGB2IN: 1.5Vp-p 28
RGB2 IN
33
R output amplitude during digital R2 input
VDRout
VDRout = Vout
70
78
86
IRE
34 RGB2IN: 1.5Vp-p 30
G output amplitude during digital G2 input
VDGout
VDGout = Vout
R, G, B out
70
78
86
IRE
35 RGB2IN: 1.5Vp-p
B output amplitude during digital B2 input
VDBout
32
VDBout = Vout
70
78
86
IRE
36 SYNCIN: composite sync GCUTOFF = 0h BCUTOFF = 0h
IK level R
VIKR
33 33 33
VIKG VIKR VIKB
0.85 0.22 0.22
1.00 0.35 0.35
1.15 0.5 0.5
V V
CXA2050S
37
IK level G
VIKG
38
IK level B
VIKB
V
Electrical Characteristics Measurement Circuit
Signal sources
are all GND unless otherwise specified in the Measurement conditions column of Electrical Characteristics.
10k 9V 100p 1k 9V
HOFF
CIN
SCL
VDRV +
HP GEN.
VPROT
YIN
CVIN
SDA
E/W
EXT SYNC IN
VIDEO OUT
VM
9V 560 500k 1 100 8.2k 0.01 4700p 47 48 47 44 46 45 43 40 0.01 42 41 39 0.1 (MPS) 100 0.1 220 1 3.3k 4700p 53 0.47 0.01 47 49 50 52 51 10k 270 0.01 100 100 330k 2.7k 820 100 10 9V 38 37 36 35 34 33 1 0.001
100
220
10
10
10
10
10
0.47 55 54
64
63
62
61
60
59
58
57
56
CIN
YIN
SCL
VM
VDRV -
VTIM
10k
SDA
HSIN
IREF
CVIN
VSIN
VSFIL
DVCC2
DGND
CERA
L2FIL
DVCC1
VTIM
AFCFIL
BLHOLD
HD OUT
DCTRAN
EXT SYNC IN
VIDEO OUT
SYNCOUT
AFCPIN/HOFF
SAWOSC
VAGCSH
E-WOUT
ABLFIL
SVCC1
SCPOUT
- (R-Y) OUT
- (B-Y) IN
R1IN
YS2
G2IN
VD + OUT/VPROT
VD - OUT/VPROT
ABLIN/VCOMP
FSC OUT
SVCC2
X443
YOUT
SGND1
- (R-Y) IN
YS1/VM
B1IN
R2IN
GSH
TEST
B2IN
APCFIL
SECAM REF
- (B-Y) OUT
YRET
SGND2
G1IN
YM
ROUT
X358
RSH
GOUT
BSH
BOUT
IKIN
IKIN
470p
4.43 MHz
3.58 MHz
SECAM REF
YOUT
FSC OUT
SCPOUT
YS1/VM
YS2
YM
RGB2 IN
ROUT
- (R-Y) OUT
- (B-Y) OUT
- (R-Y) IN
- (B-Y) IN
RGB1 IN
GOUT
BOUT
- 19 -
10 11 20 0.1 0.1 0.1 220 0.01 0.01 0.01 14 15 16 17 12 13 18 19 21 220 220 22 23 0.01 24
1
2
3
4
5
6
7
8
9
25 0.01 0.01
28 100 0.1
29
30 100 0.1
31 26 27 47 0.01
32 100 0.1
9V 51k
0.01
47
15k
470
1.5k
20k 9V 20k
9V
0.47
15p
15p
120A
CXA2050S
HP GEN.
HDOUT to AFCPIN delay 7s
5V 47 10k width12s 2000p 16 11 15 10 14 13 12 9 AFCPIN
2A
2B
VDD
2T1
2T2
2CD
1A
1B
1CD
1T2
9V 1 2 3 7 4 5 6
1T1
1Q
1Q
from HDOUT 2000p 10k
1k
1k
VSS
8
- 20 -
TC4538BP
2Q
2Q
CXA2050S
64
Application Circuit
SECAM reference input/output for SECAM IC
Color difference outputs for 1H delay line
55 10
2.2k
12
53
Sand castle pulse output
0.1
Color difference inputs from 1H delay line
17
48
YS1/VM ternary level input
0.01
2.2
5.6k 0.01
46
Analog RGB inputs
0.01 41 42
24
Analog/digital RGB inputs
30
35
RGB outputs
9V 470p 0.47 15p 18p 9V 0.022 100 0.022 100 0.022 100 470 15k
SVCC1
63
APCFIL
62
X443
61
X358
60
21
YS2 input
220
43
22
YM input
0.01
3.58MHz
TEST
59
FSC OUT
58
SECAM REF
57
SGND1
56
- (R-Y) OUT
- (B-Y) OUT
54
11
YOUT
SCPOUT
13
YRET
14
- (R-Y) IN
9V
- (B-Y) IN
330k 0.01 47 49 50 52 51
16
SGND2
YS1/VM
18
47
R1IN
19
G1IN
45
20
B1IN
YS2
YM
9V
23
R2IN
G2IN
40
25
B2IN
39
SVCC2
26 27 47 0.01
38
RSH
VD + OUT/VPROT
37
10k
28
ROUT
VD - OUT/VPROT
36
29
GSH
GOUT
31
34
BSH
33
32
BOUT
- 21 -
47 1 0.01 2 3
CIN
C signal input
0.47
EXT SYNC IN
External sync signal input
2.2
YIN
Y signal input
2.2
4.43 MHz
4
DCTRAN
0.47
1.5k 5 6 7 8 9 0.1 0.1 220 0.01 0.01 220 0.01 0.01 15
CVIN
CV signal input
2.2
BLHOLD
4.7
VIDEO OUT
CV signal or Y signal output
100
SDA
220
I2C BUS input/output
SCL
220
VM
VM output
220 100p
SYNCOUT
9V
3.3k
HSIN
470
0.0047
1
VSIN
1
100
VSFIL
DVCC2
IREF
1 10k
DGND
500k
470
CERA
AFCFIL
10k
L2FIL
Hold-down input
100
4700p
44 47 10
AFCPIN/HOFF
HP output
0.1 0.1
HD OUT
HD output
2.7k
DVCC1
SAWOSC
2
0.1
VAGCSH
0.1
100
E-WOUT
V parabola wave output
100 100
V sawtooth wave outputs V protect signal input
820
VTIM
V timing pulse output
100
ABLFIL
10
ABLIN/VCOMP
ABL/Vertical high voltage fluctuation compensation signal input IK input
1k 1
IKIN
220
1 Metal film resistor recommended 2 MPS capacitor recommended
0.001
CXA2050S
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA2050S
Electrical Characteristics Measurement Conditions "I2C Bus Register Initial Settings" Register name PICTURE TRAPOFF VM HUE DCTRAN D-PIC COLOR TOT ABL BRIGHT D-COL LIMIT SHARPNESS PRE-OVER COLOR SW SUB-CONT TRAP F0 SUB-COLOR SUB-HUE SUB-BRIGHT GAMMA G-DRIVE AGING B-DRIVE INTERLACE G-CUTOFF B-CUTOFF RON GON BON PICON VOFF FHHI CD-MODE AKBOFF V-SIZE No. of Initial setting bits 6 1 1 6 1 1 6 1 1 6 1 1 4 2 2 4 4 4 4 6 2 6 1 6 2 4 4 1 1 1 1 1 1 1 1 6 3Fh 1h 1h 1Fh 0h 0h 1Fh 0h 0 1Fh 0h 0 7h 3h 0h 7h 7h 7h 7h 1Fh 0h 2Ah 0h 2Ah 0h 0h 0h 1h 1h 1h 1h 0h 0h 0h 0h 1Fh Description Maximum value TRAP off Maximum value Center value DCTRAN off DPIC off Center value TOT off Picture/bright ABL mode Center value DCOL off Limiter off Center value Maximum value Automatic switching Center value Center value Center value Center value Center value Minimum value Center value AGING off Center value Interlace Minimum value Minimum value R output on G output on B output on Picture mute off VD output on FH normal Automatic switching AKB on Center value - 22 - Register name V FREQ V-POSITION AFC-MODE S-CORR V-LIN H-SIZE REF-POSI PIN-COMP VBLKW H-POSITOPN PIN-PHASE AFC-BOW AFC-ANGLE EHT H EHT V XTAL EXT SYNC CV/YC V-ASPECT ZOOM SW HBLKSW V-SCROLL JMPSW HSIZESW UP-VLIN LO-VLIN LEFT-BLK RIGHT-BLK UP-CPIN LO-CPIN CDMODE2 SHPF0 YS1OFF DL No. of Initial setting bits 2 6 2 4 4 6 2 6 2 4 4 4 4 2 2 2 1 1 6 1 1 6 1 1 4 4 4 4 4 4 1 1 1 3 0h 1Fh 1h 0h 7h 1Fh 3h 1Fh 0h 7h 7h 7h 7h 0h 0h 0h 0h 0h 0h 0h 0h 1Fh 0h 0h 0h 0h 7h 7h 7h 7h 0 0 0h 3h Description Automatic switching Center value Low gain Minimum value Center value Center value Maximum value Center value Minimum value Center value Center value Center value Center value EHT H off EHT V off Automatic switching Internal sync CV input Minimum value ZOOM SW off HBLKSW off Center value JMPSW off HSIZESW off Minimum value Minimum value Center value Center value Center value Center value Standard mode 3MHz YS1 normal Center value
CXA2050S
Definition of I2C Bus Registers Slave Addresses 88h: Slave Receiver 89h: Slave Transmitter Register Table "": Undefined Control Register Sub Address x x x 0 0 0 0 0 00 h x x x 0 0 0 0 1 01 h x x x 0 0 0 1 0 02 h x x x 0 0 0 1 1 03 h x x x 0 0 1 0 0 04 h x x x 0 0 1 0 1 05 h x x x 0 0 1 1 0 06 h x x x 0 0 1 1 1 07 h x x x 0 1 0 0 0 08 h x x x 0 1 0 0 1 09 h x x x 0 1 0 1 0 0A h x x x 0 1 0 1 1 0B h x x x 0 1 1 0 0 0C h x x x 0 1 1 0 1 0D h x x x 0 1 1 1 0 0E h x x x 0 1 1 1 1 0F h x x x 1 0 0 0 0 10 h x x x 1 0 0 0 1 11 h x x x 1 0 0 1 0 12 h x x x 1 0 0 1 1 13 h x x x 1 0 1 0 0 14 h x x x 1 0 1 0 1 15 h x x x 1 0 1 1 0 16 h x x x 1 0 1 1 1 17 h x x x 1 1 0 0 0 18 h x x x 1 1 0 0 1 19 h UP-VLIN LEFT-BLK UP-CPIN CDMODE2 SHPF0 YS1 OFF EHT H RON G-CUTOFF GON BON PICON VOFF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 TRAPOFF DC-TRAN TOT D-COL PRE-OVER Bit0 VM D-PIC ABL LIMIT
PICTURE HUE COLOR BRIGHT SHARPNESS SUB-CONT SUB-COLOR SUB-BRIGHT G-DRIVE B-DRIVE
COLOR SW TRAP F0
SUB-HUE GAMMA AGING 0
INTERLACE B-CUTOFF FHHI CD-MODE AKBOFF V-FREQ AFC-MODE V-LIN
V-SIZE V-POSITION S-CORR H-SIZE PIN-COMP H-POSITION AFC-BOW EHT V V-ASPECT V-SCROLL XTAL PIN-PHASE
REF-POSI VBLKW
AFC-ANGLE EXT SYNC CV/YC ZOOM SW HBLKSW JMP SW HSIZESW LO-VLIN RIGHT-BLK LO-CPIN DL
Status Register Bit7 H LOCK Bit6 IKR Bit5 VNG - 23 - Bit4 XRAY Bit3 Bit2 Bit1 FSC Bit0 FV
COLOR SYS
CXA2050S
Description of Registers Register name (No. of bits) 1. Video switch register CV/YC (1) : CV input/YC input selector 0 = CV input selected 1 = YC input selected : EXT SYNC selector switch 0 = Internal sync (CV or Y) selected 1 = EXT SYNC selected
EXT SYNC
(1)
2. Y signal block register SUB-CONT (4) : Contrast gain control (Y gain control) 0h = -3.5dB 7h = 0dB Fh = +2.5dB : Chroma trap f0 fine adjustment 0h = High 7h = Center Fh = Low : Sharpness gain control 0h = -6dB 7h = +2.5dB Fh = +6.5dB : Sharpness f0 selector 0 = 3MHz 1 = 3.5MHz : Sharpness preshoot/overshoot ratio control 0h = 1:1 (PRE: OVER) 3h = 2:1 : Y differential signal output level selector for VM (for 100% 3MHz input) 0 = 1.1Vp-p 1 = 2.65Vp-p : Y block chroma trap ON/OFF 0 = Trap ON 1 = Trap OFF : Y signal delay time control (80ns/step) 0h = Max. 7h = Min. - 24 -
TRAP-F0
(4)
SHARPNESS (4)
SHPF0
(1)
PRE-OVER
(2)
VM
(1)
TRAP OFF
(1)
DL
(3)
CXA2050S
DC-TRAN
(1)
: Y DC transmission ratio selector switch 0 = 100% 1 = 81% : Y black expansion ON/OFF switch 0 = OFF 1 = ON Point of inflection: 30 IRE
D-PIC
(1)
3. C signal block register TOT (1) : Chroma TOT filter band selector switch 0 = TOT -- TRAP OFF 1 = TOT -- TRAP ON (TRAP fo 2MHz) : Color gain control (Chroma gain control) 0h = Color OFF (-40dB or less) 1Fh = 0dB B output: 1.02Vp-p (I/O gain: +11dB, 0.285Vp-p input) 3Fh = +6dB : Color gain control (ACC reference level control) 0h = -5dB 7h = 0dB Fh = +3dB : Hue control (Phase control for chroma demodulation axis when SUB-HUE is 7h) Control not possible for a PAL system. 0h = +35 Flesh color appears red. 1Fh = 0 3Fh = -35 Flesh color appears green. : Hue control (Phase control for chroma demodulation axis when HUE is 1Fh) B-Y axis adjustable to 0. Control not possible for a PAL system. 0h = +10 7h = 0 Fh = -10 : XTAL selection setting switch 0h = Automatic identification 1h = Force to XTAL1 (3.58MHz) 2, 3h = Force to XTAL2 (4.43MHz) : Color system setting 0h = Automatic identification 1h = Force to PAL 2h = Force to NTSC 3h = Force to SECAM - 25 -
COLOR
(6)
SUB-COLOR (4)
HUE
(6)
SUB-HUE
(4)
XTAL
(2)
COLOR SW
(2)
CXA2050S
4. RGB signal block register PICTURE (6) : Picture gain control (RGB gain control) 0h = -14dB 3Fh = 0dB RGB output: 2.5Vp-p (I/O gain: +8dB, 1Vp-p input) : Bright control (RGB DC bias control) 0h = -420mV 1Fh = 0mV (-300mV for REF-P level) 3Fh = +420mV : Bright control (RGB DC bias control) 0h = -420mV 1Fh = 0mV (-300mV for REF-P level) 3Fh = +420mV : Gch drive gain adjustment (Gch gain control) 0h = G/R -4.5dB 2Ah = G/R 0dB (G/R 0dB) 3Fh = G/R +1.5dB : Bch drive gain adjustment (Bch gain control) 0h = B/R -4.5dB 2Ah = B/R 0dB (B/R 0dB) 3Fh = B/R +1.5dB : Gch cut-off adjustment (Gch reference pulse value control of IKIN pin input) 0h = +34% 7h = +81% (G/R) Fh = +135% : Bch cut-off adjustment (Bch reference pulse value control of IKIN pin input) 0h = +34% 7h = +81% (B/R) Fh = +135% : Dynamic color ON/OFF switch 0 = Dynamic color OFF 1 = Dynamic color ON (R, Bch level control) : Gamma control (RGB gamma correction amount control) 0h = Gamma OFF 3h = Gamma peak 17 IRE (at input 40 IRE), +400mV (at 2.5Vp-p OUT)
BRIGHT
(6)
SUB-BRIGHT (6)
G-DRIVE
(6)
B-DRIVE
(6)
G-CUTOFF
(4)
B-CUTOFF
(4)
D-COL
(1)
GAMMA
(2)
- 26 -
CXA2050S
REF-POSITION (2)
: Reference pulse timing setting 0h = From rising edge of V TIM: Rch 22H, Gch 23H, Bch 24H 1h = From rising edge of V TIM: Rch 20H, Gch 21H, Bch 22H 2h = From rising edge of V TIM: Rch 18H, Gch 19H, Bch 20H 3h = From rising edge of V TIM: Rch 16H, Gch 17H, Bch 18H : ON/OFF switch for RGB output with a reference pulse (Set to OFF mode at power-on.) 0 = RGB output OFF (All blanked status) 1 = RGB output ON : ON/OFF switch for Rch video output without a reference pulse (Operates when PIC ON = 1, set to OFF mode at power-on.) 0 = Rch video output OFF (Blanked status, reference pulse only output) 1 = Rch video output ON : ON/OFF switch for Gch video output without a reference pulse (Operates when PIC ON = 1, set to OFF mode at power-on.) 0 = Gch video output OFF (Blanked status, reference pulse only output) 1 = Gch video output ON : ON/OFF switch for Bch video output without a reference pulse (Operates when PIC ON = 1, set to OFF mode at power-on.) 0 = Bch video output OFF (Blanked status, reference pulse only output) 1 = Bch video output ON : AKB ON/OFF switch (Set to ON mode at power-on.) 0 = AKB ON 1 = AKB OFF (IK CLAMP, IK S/H and reference pulse fixed to OFF) R, G and B cut-off adjustment at AKB OFF performed by voltage applied to RSH, GSH and BSH pins, respectively. : YS1 forced OFF mode/YS1 normal mode 0 = YS1 normal mode 1 = YS1 forced OFF mode : ABL mode selector 0 = Picture/bright ABL mode 1 = Picture ABL mode : Peak limiter (RGBOUT pin is limited at DC5.2V) 0 = OFF 1 = ON
PIC-ON
(1)
R ON
(1)
G ON
(1)
B ON
(1)
AKB OFF
(1)
YS1 OFF
(1)
ABL
(1)
LIMIT
(1)
- 27 -
CXA2050S
5. Deflection block register AFC-MODE (2) : AFC loop gain control (PLL between H SYNC and H VCO) 0h = H free run mode 1h = Small gain 2h = Medium gain 3h = Large gain : H oscillator frequency fixation ON/OFF switch (Set to ON mode at power-on.) 0 = H oscillator frequency fixation OFF AFC normal mode 1 = H oscillator frequency fixation ON Oscillator frequency fixed to maximum value (approx. 16.2kHz) : V frequency mode setting 0, 1h = Automatic identification 2h = Forced mode (50Hz) 3h = Forced mode (60Hz) : V sawtooth wave oscillation stop ON/OFF switch (Set to OFF mode at power-on.) 0 = Oscillation stop OFF (V DRIVE- and V DRIVE+: normal output) 1 = Oscillation stop ON (V DRIVE- and V DRIVE+: DC output and DC value vary according to V POSITION.) : V countdown system mode selector (Set to automatic selection mode during power-on.) 0 = Non-standard signal mode, standard signal mode and no signal mode automatically selected 1 = Fixed to non-standard signal mode (V oscillator frequency is 55Hz during no signal mode "free run".) : Vertical sync pull-in speed selector 0 = Standard 1 = High speed : VBLK width control (Blanked pulses after reference pulse. Operates when JMPSW = 1; blanked pulses after reference pulse fixed to 1H when JMPSW = 0.) 0h = 12H from Bch reference pulse 1h = 11H from Bch reference pulse 2h = 10H from Bch reference pulse 3h = 9H from Bch reference pulse : Horizontal position adjustment (HAFC phase control) 0h = 1s delay Picture position shifts to right. (Picture delayed with respect to HD.) 7h = 0s Fh = 1s advance Picture position shifts to left. (Picture advanced with respect to HD.) : Vertical position adjustment (V SAW output DC bias control) 0h = -0.09V Picture position drops, V DRIVE+ output DC Down. 1Fh = 0V Center potential: DC 3V 3Fh = +0.09V Picture position rises, V DRIVE+ output DC Up. - 28 -
FH-HI
(1)
V FREQ
(1)
V OFF
(1)
CD-MODE
(1)
CDMODE2
(1)
VBLKW
(2)
H-POSITION (4)
V-POSITION
(6)
CXA2050S
V-SIZE
(6)
: Vertical amplitude adjustment (V SAW output gain control) 0h = -14% Vertical picture size decreases. 1Fh = 0% Amplitude: 1.23Vp-p, center potential: DC 3V when V-ASPECT is 2Fh. 3Fh = +14% Vertical picture size increases. : Vertical linearity adjustment (Gain control for V SAW secondary component) 0h = 115% (Bottom/top of picture) Top of picture compressed; bottom of picture expanded. 7h = 100% (Bottom/top of picture) Fh = 85% (Bottom/top of picture) Top of picture expanded; bottom of picture compressed. : Vertical S correction amount adjustment (V SAW secondary component gain control) 0h = Secondary component amplitude by adding sawtooth = 0 Fh = Secondary component amplitude by adding sawtooth = Maximum : Vertical line bow compensation amount adjustment (Phase control according to HAFC parabola wave) 0h = Top and bottom of picture delayed 500ns with respect to picture center. 7h = 0 ns Fh = Top and bottom of picture advanced 500ns with respect to picture center. : Vertical line slope compensation amount adjustment (Phase control according to HAFC V SAW) 0h = Top of picture delayed 400ns, bottom of picture advanced 400ns with respect to picture center. 7h = 0 ns Fh = Top of picture advanced 400ns, bottom of picture delayed 400ns with respect to picture center. : Horizontal pin distortion compensation amount adjustment (V parabola wave gain control) 0h = 0.10Vp-p Horizontal size for top/bottom of picture increases. (Compensation amount minimum) 1Fh = 0.58Vp-p Amplitude, center potential: DC 4V when V-ASPECT is 0h 3Fh = 1.06Vp-p Horizontal size for top/bottom of picture decreases. (Compensation amount maximum) : Horizontal amplitude adjustment (V parabola wave DC bias control) 0h = -0.5V Horizontal picture size decreases, EW-DRIVE output DC Down. 1Fh = 0V Amplitude: 0.58Vp-p, center potential: DC 4 V when V-ASPECT is 2Fh 3Fh = +0.5V Horizontal picture size increases, EW-DRIVE output DC Up. : Horizontal high-voltage fluctuation compensation amount setting (DC adjustment for parabolic output) 0h = 0V (Compensation amount when 1V is applied to ABL IN versus 8V applied to ABL IN) 3h = -0.1V (Compensation amount when 1V is applied to ABL IN versus 8V applied to ABL IN) : Vertical high-voltage fluctuation compensation amount setting (V SAW output gain control) 0h = 0% (Compensation amount when 1V is applied to ABL IN versus 8V applied to ABL IN) 3h = -7% (Compensation amount when 1V is applied to ABL IN versus 8V applied to ABL IN) : Interlace mode and non-interlace display selector switch 0,1h = Interlace mode 2h = Interlace mode; 1/2H shift applied to EVEN lines 3h = Interlace mode; 1/2H shift applied to ODD lines - 29 -
V-LIN
(4)
S-CORR
(4)
AFC-BOW
(4)
AFC-ANGLE
(4)
PIN-COMP
(6)
H-SIZE
(6)
EHT-H
(2)
EHT-V
(2)
INTERLACE
(1)
CXA2050S
PIN-PHASE
(4)
: Horizontal trapezoidal distortion compensation amount adjustment (V parabola wave center timing control) 0h = 0.8ms advance Horizontal size for top of picture increases; horizontal size for bottom of picture decreases. 7h = 0ms 8.9ms from 4VDC VTIM Fh = 0.8ms delay Horizontal size for top of picture decreases; horizontal size for bottom of picture increases. : Horizontal pin distortion compensation amount adjustment for top of picture (V parabola wave gain control: Func.) 0h = +0.6V Horizontal size for top of picture increases. (compensation amount minimum) 7h = 0V (0.7Vp-p 4:3 mode) Fh = -0.6V Horizontal size for top of picture decreases. (compensation amount maximum) : Horizontal pin distortion compensation amount adjustment for bottom of picture (V parabola wave gain control: Func.) 0h = +0.5V Horizontal size for bottom of picture increases. (compensation amount minimum) 7h = 0V (0.7Vp-p 4:3 mode) Fh = -0.5V Horizontal size for bottom of picture decreases. (compensation amount maximum) : Aspect ratio control (Gain control for sawtooth wave) 0h = 75% 16:9 CRT full 2Fh = 100% 4:3 CRT full, amplitude: 1.32Vp-p 3Fh = 112% : Zoom mode ON/OFF switch for 16:9 CRT (25% of video cut) 0 = Zoom OFF Sawtooth wave amplitude: 1.32Vp-p 1 = Zoom ON Sawtooth wave amplitude: 70% : HBLK width control ON/OFF switch during 4:3 software full display mode on a 16:9 CRT 0 = Control OFF HBLK pulse generated from HPIN. 1 = Control ON HBLK pulse generated as pulse generated from HPIN or as pulse generated from HVCO and width adjusted. Width adjustment is performed by the LEFT-BLK and RIGHT-BLK registers. : Vertical picture scroll control during zoom mode on a 16:9 CRT (DC component added to sawtooth wave AGC output to control ZOOMSW cut timing.) 0h = -0.2V Scrolled toward top of screen by 32H and top of picture zoomed. 1Fh = 0V 3Fh = +0.2V Scrolled toward bottom of screen by 32H and bottom of picture zoomed. : Reference pulse jump mode ON/OFF switch (In addition to V-ASPECT control, sawtooth wave gain control performed for 100% of VBLK interval and 67% of picture interval) 0 = Jump mode OFF 1 = Jump mode ON On a 4:3 CRT, jump mode expands the sawtooth wave amplitude to 112% with VASPECT; on a 16:9 CRT, jump mode compresses the sawtooth wave amplitude to 75% with V-ASPECT. The V blanking width is expanded at both the top and bottom of the picture. Blanking for the bottom of the picture starts 251H after VTIM, and blanking for the top of the picture can be varied as the blanking width after the reference pulse from the VBLKW register. - 30 -
UP-CPIN
(4)
LO-CPIN
(4)
V-ASPECT
(6)
ZOOM SW
(1)
HBLKSW
(1)
V-SCROLL
(6)
JUMPSW
(1)
CXA2050S
HSIZESW
(1)
: Lowers the E-W OUT DC level (during H-SIZE compression) 0 = Normal 1 = -1.35V : Vertical linearity adjustment for top of picture (Secondary component gain control for sawtooth wave added to sawtooth wave AGC output) 0h = 100% (Bottom/top of picture) Fh = 115% (Bottom/top of picture) Top of picture compressed. : Vertical linearity adjustment for bottom of picture (Tertiary component gain control for sawtooth wave added to sawtooth wave AGC output) 0h = 100% (Bottom/top of picture) Fh = 75% (Bottom/top of picture) Bottom of picture compressed. : HBLK width control for the left side of picture when HBLKSW = 1 (Phase control for timing pulse generated from HVCO) 0h = +1.7s HBLK width maximum 7h = 0s Center HBLK: 15s Fh = -1.7s HBLK width minimum : HBLK width control for the right side of picture when HBLKSW = 1 (Phase control for timing pulse generated from HVCO) 0h = +1.7s HBLK width maximum 7h = 0s Center HBLK: 15s Fh = -1.7s HBLK width minimum
UP-VLIN
(4)
LO-VLIN
(4)
LEFT-BLK
(4)
RIGHT-BLK
(4)
6. Other AGING (1) : White output aging mode ON/OFF switch (Takes priority over RGB ON and PIC ON control. Set to OFF mode at power-on.) 0 = Aging mode OFF 1 = Aging mode ON (When there is no input signal, a 60 IRE flat signal is output from the Y block)
- 31 -
CXA2050S
7. Status register HLOCK (1) : Lock status between H SYNC and H VCO 0 = HVCO free run status 1 = Locked to H SYNC : AKB operation status 0 = REF-P at Ik small and AKB loop unstable. 1 = REF-P at Ik sufficient and AKB loop stable. : Signal input status to V PROT pin 0 = No V PROT input 1 = V PROT input (In this case, the RGB output is blanked.) : Signal input status to XRAY control pin (HOFF pin) 0 = No XRAY control input 1 = XRAY control input (In this case, the RGB output is blanked.) : Color system status 0h = PAL 1h = NTSC 2h = SECAM 3h = NO STANDARD : X'tal status (Fsc information) 0 = 4.43MHz 1 = 3.58MHz : Vertical deflection frequency status 0 = 50Hz 1 = 60Hz
IKR
(1)
VNG
(1)
XRAY
(1)
COLOR SYS (2)
FSC
(1)
FV
(1)
- 32 -
CXA2050S
Description of Operation 1. Power-on sequence The CXA2050S does not have an internal power-on sequence. Therefore, power-on sequence is all controlled by the set microcomputer (I2C bus controller). 1) Power-on The IC is reset and the RGB outputs are all blanked. Hdrive starts to oscillate, but oscillation is at the maximum frequency (16kHz or more) and is not synchronized to the input signal. Output of vertical signal VTIM starts, but Vdrive is DC output. Bus registers which are set by power-on reset are as follows. AGING RON GON BON PICON VOFF VFREQ FHHI HSIZESW CD-MODE AKBOFF = 0: All white output aging mode OFF = 0: Rch video blanking ON = 0: Gch video blanking ON = 0: Bch video blanking ON = 0: RGB all blanking ON = 1: VDRIVE output stopped mode = 0: Automatic identification mode (identification starts at 50Hz) = 1: H oscillator maximum frequency mode = 0: Normal = 0: Automatic selector mode of the countdown mode = 0: AKB mode
2) Bus register data transfer The register setting sequence differs according to the set sequence. Register settings for the following sequence are shown as an example. Set sequence Power-on Degauss VDRIVE oscillation CXA2050S register settings Reset status in 1) above. Reset status in 1) above. The CRT is degaussed in the completely darkened condition. The IC is set to the power-on initial settings. (See the following page.) A sawtooth wave is output to VDRIVE and the IC waits for the vertical deflection to stabilize. The HDRIVE oscillator frequency goes to the standard frequency. PICON is set to 1 and a reference pulse is output from Rout, Gout and Bout. Then, the IC waits for the cathode to warm up and the beam current to start flowing. Status register IKR is monitored. IKR = 0: No cathode current IKR = 1: Cathode current Note that the time until IKR returns to 1 differs according to the initial status of the cathode. RON, GON and BON are set to 1 and the video signal is output from Rout, Gout and Bout. - 33 -
AKB operation start
AKB loop stable
Video output
CXA2050S
I2C bus power-on initial settings The initial settings listed here for power-on when VDRIVE starts to oscillate are reference values; the actual settings may be determined as needed according to the conditions under which the set is to be used. Register Table "" Undefined Control Register Sub Address x x x 0 0 0 0 0 00 h x x x 0 0 0 0 1 01 h x x x 0 0 0 1 0 02 h x x x 0 0 0 1 1 03 h x x x 0 0 1 0 0 04 h x x x 0 0 1 0 1 05 h x x x 0 0 1 1 0 06 h x x x 0 0 1 1 1 07 h x x x 0 1 0 0 0 08 h x x x 0 1 0 0 1 09 h x x x 0 1 0 1 0 0A h x x x 0 1 0 1 1 0B h x x x 0 1 1 0 0 0C h x x x 0 1 1 0 1 0D h x x x 0 1 1 1 0 0E h x x x 0 1 1 1 1 0F h x x x 1 0 0 0 0 10 h x x x 1 0 0 0 1 11 h x x x 1 0 0 1 0 12 h x x x 1 0 0 1 1 13 h x x x 1 0 1 0 0 14 h x x x 1 0 1 0 1 15 h x x x 1 0 1 1 0 16 h x x x 1 0 1 1 1 17 h x x x 1 1 0 0 0 18 h x x x 1 1 0 0 1 19 h Bit7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit6 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 Bit5 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 Bit4 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 Bit3 1 1 1 1 0 0 0 1 1 1 0 0 1 1 0 1 1 0 0 0 0 1 0 1 0 0 Bit2 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 0 Bit1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 1 1 Bit0 1 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1
- 34 -
CXA2050S
3) Power-on initial settings The initial settings listed here for power-on when VDRIVE starts to oscillate are reference values; the actual settings may be determined as needed according to the conditions under which the set is to be used. PICTURE = 3Fh Max. (User Control) TRAP OFF =0 Chroma Trap ON VM =1 2.65Vp-p (User Control) HUE = 1Fh Center (User Control) DC-TRAN =0 Y DC transmission ratio 100% D-PIC =1 Y black expansion ON COLOR = 1Fh Center (User Control) TOT =0 Chroma low frequency increased ABL =0 Picture/Bright ABL mode BRIGHT = 1Fh Center (User Control) D-COL =1 Dynamic Color ON LIMIT =1 Peak Limiter ON SHARPNESS = 7h Center (User Control) PRE-OVER =0 Sharpness pre/over ratio 1:1 COLOR SW = 0 AUTO SUB-CONT = 7h Center (Adjust) TRAP F0 = 7h Center (Adjust) SUB-COLOR = 7h Center (Adjust) SUB-HUE = 7h Center (Adjust) SUB-BRIGHT = 1Fh Center (Adjust) GAMMA =0 Gamma OFF G-DRIVE = 1Fh Center (Adjust) AGING =0 Aging Mode OFF B-DRIVE = 1Fh Center (Adjust) INTERLACE = 0 INTERLACE mode G-CUTOFF = 7h Center (Adjust) B-CUTOFF = 7h Center (Adjust) RON =0 Rch video output OFF GON =0 Gch video output OFF BON =0 Bch video output OFF PICON =0 RGB all blanked VOFF =0 Vdrive oscillation FHHI =0 Horizontal oscillator frequency standard CD-MODE =0 V countdown auto mode AKBOFF =0 AKB ON V-SIZE = 1Fh Center (Adjust) V-FREQ =0 AUTO V-POSITION = 1Fh Center (Adjust) AFC-MODE = 2 Center S-CORR = 7h Center (Adjust) V-LIN = 7h Center (Adjust) H-SIZE = 1Fh Center (Adjust) REF-POSI =0 PIN-COMP = 1Fh Center (Adjust) - 35 -
CXA2050S
(Power-on initial settings cont.) H-POSITION PIN-PHASE AFC-BOW AFC-ANGLE EHT-H EHT-V XTAL EXT SYNC CV/YC V-ASPECT ZOOMSW HBLKSW V-SCROLL JMPSW HSIZE SW UP-VLIN LO-VLIN LEFT-BLK RIGHT-BLK UP-CPIN LO-CPIN CDMODE2 SHPF0 YS1 OFF DL = 7h = 7h = 7h = 7h =0 =3 =0 =0 =0 = 0h =1 =1 = 1Fh =0 =0 = 7h = 7h = Fh = Fh = 7h = 7h =0 =1 =0 =3 Center (Adjust) Center (Adjust) Center (Adjust) Center (Adjust) H drive high-voltage compensation OFF V drive high-voltage compensation amount maximum AUTO Internal SYNC CV input 16:9 CRT Full Mode 16:9 CRT Hblk width adjust ON Center (User Control) 16:9 CRT Full Mode Normal 16:9 CRT Full Mode 16:9 CRT Full Mode Hblk width Min. (Adjust) Hblk width Min. (Adjust) Center (Adjust) Center (Adjust) Standard Sharpness F0 3.5MHz Normal Normal (Adjust)
2. Various mode settings The CXA2050S contains bus registers for deflection compensation which can be set for various wide modes. Wide mode setting registers can be used separately from registers for normal picture distortion adjustment, and once deflection adjustment has been performed in full mode, wide mode settings can be made simply by changing the corresponding register data. * VDRIVE signal picture distortion adjustment registers V-SIZE, V-POSITION, S-CORR, V-LIN * E/WDRIVE signal picture distortion adjustment registers H-SIZE, PIN-COMP, PIN-PHASE, UP-CPIN, LO-CPIN * Wide mode setting registers V-ASPECT, ZOOMSW, HBLKSW, V-SCROLL, JMPSW, HSIZESW, UP-VLIN, LO-VLIN, LEFT-BLK, RIGHT-BLK
- 36 -
CXA2050S
Examples of various modes are listed below. These modes are described using 570 (NTSC: 480) lines as the essential number of display scanning lines. Wide mode setting register data is also listed, but settings may differ slightly due to IC variation. The standard setting data differs for 16:9 CRTs and 4:3 CRTs. Register V-ASPECT V-SCROLL ZOOMSW UP-VLIN LO-VLIN JMPSW HSIZESW HBLKSW LEFT-BLK RIGHT-BLK 16:9 CRT 0h 1Fh 1 0h 0h 0 0 1 7h 7h 4:3 CRT 2Fh 1Fh 0 0h 0h 0 0 1 7 7h
1) 16:9 CRT full mode This mode reproduces the full 570 (NTSC:480) lines on a 16:9 CRT. 4:3 images are reproduced by stretching the picture to the left and right. Normal images are compressed vertically, but 16:9 images can be reproduced in their original 16:9 aspect ratio with a video source which compresses (squeezes) 16:9 images to 4:3 images. The register settings are the 16:9 CRT standard values. 2) 16:9 CRT normal mode In this mode, 4:3 images are reproduced without modification. A black border appears at the left and right of the picture. In this mode, the H deflection size must be compressed by 25% compared to full mode. The CXA2050S permits compression with a register (HSIZESW) that compresses the H size by 25%. Because excessive current flows to the horizontal deflection coil in this case, adequate consideration must be given to the allowable power dissipation, etc., of the horizontal deflection coil in the design of the set. In addition, this concern can also be addressed through measures taken external to the IC, such as by switching the horizontal deflection coil. Full mode should be used when using memory processing to add a black border to the video signal. H blanking of the image normally uses the flyback pulse input to AFCPIN (Pin 44). However, the blanking width can be varied according to the control register setting when blanking is insufficient for the right and left black borders. The following three settings are added to the 16:9 CRT standard values for the register settings. HBLKSW = 1 LEFT-BLK = Adjustment value RIGHT-BLK = Adjustment value The H angle of deflection also decreases, causing it to differ from the PIN compensation amount during H size full status. Therefore, in addition to the wide mode registers, PIN-COMP must also be readjusted only for this mode. 3) 16:9 CRT zoom mode In this mode, 4:3 images are reproduced by enlarging the picture without other modification. The top and bottom of normal 4:3 images are lost, but almost the entire picture can be reproduced for vista size video software, etc. which already has black borders at the top and bottom. The enlargement ratio can be controlled by the V-ASPECT register, and enlarging the picture by 33% compared to full mode allows zooming to be performed for 4:3 images without distortion. In this case, the number of scanning lines is reduced to 430 lines compared to 570 lines for full mode. The zooming position can be shifted vertically by the V-SCROLL register. V blanking of the image normally begins from V sync and continues for 2H after the AKB reference pulse, and the top and bottom parts are also blanked during this mode. Adjust the following two registers with respect to the 16:9 CRT standard values for the register settings. V-ASPECT = 2Fh V-SCROLL = 1Fh or user control - 37 -
CXA2050S
4) 16:9 CRT subtitle-in mode When CinemaScope size images which have black borders at the top and bottom of the picture are merely enlarged with the zoom mode in 3) above, subtitles present in the black borders may be lost. Therefore, this mode is used to super-compress only the subtitle part and reproduce it on the display. Add the LO-VLIN adjustment to the zoom mode settings for the register settings. V-ASPECT = 2Fh V-SCROLL = 1Fh or user control LO-VLIN = Adjustment value The LO-VLIN register causes only the linearity at the bottom of the picture to deteriorate. Therefore, UP-VLIN should also be adjusted if the top and bottom of the picture are to be made symmetrical. Since the picture is compressed vertically, the number of scanning lines exceeds 430 lines. 5) 16:9 CRT V compression mode This mode is used to reproduce two 4:3 video displays such as for PandP. The V size must be compressed to 67% in order to reproduce two displays on a 16:9 CRT without distortion using 480 scanning lines, and this can be set by JMPSW. Compression is performed after the AKB reference pulse, so the reference pulse remains in the overscan position. The V blanking width after the reference pulse becomes larger than normal and can be varied by the VBLKW register. During this mode, the bottom V blanking width is also expanded to 3H wider than normal so that the bottom of the picture is not overscanned. 16:9 CRT standard values are used with only the JMPSW setting changed for the register settings. JMPSW = 1 6) 16:9 CRT wide zoom mode This mode reproduces 4:3 video software naturally on wide displays by enlarging 4:3 images without other modification and compressing the parts of the image which protrude from the picture into the top and bottom parts of the picture. The display enlargement ratio is controlled by V-ASPECT, and the compression ratios at the top and bottom of the picture are controlled by UP-VLIN and LO-VLIN. Adjust the following three registers with respect to the 16:9 CRT standard values for the register settings. V-ASPECT = Adjustment value UP-VLIN = Adjustment value LO-VLIN = Adjustment value 7) 4:3 CRT normal mode This is the standard mode for 4:3 CRTs. The register settings are the 4:3 CRT standard values. 8) 4:3 CRT V compression mode This mode is used to reproduce M-N converter output consisting of 16:9 images expanded to a 4:3 aspect ratio and other squeezed signals without distortion on a 4:3 CRT. The V size must be compressed to 75% in order to reproduce a 4:3 squeezed signal at a 16:9 aspect ratio without any distortion. Compressing the V size with the JMPSW register used in mode 5) above, compresses the V size to 67%. Therefore, V-ASPECT is set to enlarge the V size by 8%. AKB reference pulse handling and V blanking are the same as for mode 5) above. 4:3 CRT standard values are used with the V-ASPECT and JMPSW settings changed for the register settings. V-ASPECT = 3Fh JMPSW =1
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CXA2050S
Mode Settings Setting CRT SIZE SOFT SIZE 1)-1 1)-2 16:9 16:9 16:9 4:3 MODE NAME 16:9 CRT full Wide full I2C BUS REGISTER V-ASPECT = 0h: V size 75% V-ASPECT = 0h: V size 75% V-ASPECT = 0h: V size 75% HBLKSW = 1h: HBLK width adjustment ON LEFT-BLK = Adjustable RIGHT-BLK = Adjustable PIN-COMP = Adjustable (External support: H-DY H amplitude 75%) V-ASPECT = 2Fh: V size 100% ZOOMSW = 1h: Zoom ON V size limited at 75% V-SCROLL = 0h: Zoom bottom of video image 1Fh: Zoom center of video image 3Fh: Zoom top of video image Adjustable: Open to user V-ASPECT = 2Fh: V size 100% UP-VLIN = Adjustable: Slightly compresses top of video image LO-VLIN = Adjustable: Significantly compresses bottom of video image ZOOMSW 1h: V size limited at 75% (V-SCROLL = Adjustable) V-ASPECT = 0h: V size 75% JMPSW = 1h: Reference pulse skipping ON V size compressed 67% after the reference pulse (compressed to 50% total) VBLKW = Adjustable: VBLK width expanded at top and bottom of video image V-ASPECT = Adjustable: V size 90% UP-VLIN = Adjustable: Compression of top and LO-VLIN = Adjustable: bottom of video image (S-CORR = Adjustable): V-ASPECT = 2Fh: V size 100% V-ASPECT = 3Fh: V size 112% JMPSW = 1h: Reference pulse skipping ON (compressed to 75% total) VBLKW = Adjustable: VBLK width expanded at top and bottom of video image
2)
16:9
4:3
16:9 CRT normal
3)
16:9
4:3
16:9 CRT zoom
4)
16:9
4:3 (16:9 + subtitle area)
16:9 CRT with subtitle area on
5)
16:9
4:3
16:9 CRT V compression
6)
16:9
4:3
16:9 CRT wide zoom 4:3 CRT normal
7)
4:3
4:3
8)
4:3
16:9
4:3 CRT V compression
The amount of picture distortion compensation in a vertical direction position of the CRT does not change in response to the above modes; as a result, the initial values of each picture distortion register can be used as it is.
- 39 -
CXA2050S
3. Signal processing The CXA2050S is comprised of sync signal processing, H deflection signal processing, V deflection signal processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I2C bus. 1) Sync signal processing Pin 54 (SYNC OUT) outputs at 2Vp-p either the internal signal (CVIN/YIN) selected by the internal video switch, or the external sync signal input from Pin 63 (EXT SYNC IN). This selection is controlled by the I2C bus. The signal output from Pin 54 is buffered by a PNP Tr. and is then input to HSIN (Pin 53) or VSIN (Pin 52) through a suitable filter. The Y signals input to Pins 52 and 53 are sync separated by the horizontal and vertical sync separation circuits. The resulting horizontal sync signal and the signal (FH = 15625Hz or 15734Hz) obtained by frequency dividing the 32FH-VCO output using the ceramic oscillator (frequency 500kHz or 503.5kHz) by 32 are phasecompared, the AFC loop is constructed, and an H pulse synchronized with the H sync is generated inside the IC. Adjustment of the H oscillator frequency is unnecessary. When the AFC is locked to the H sync, 1 is output to the status register (HLOCK) and that can be used to detect the presence of the video signal. The vertical sync signal is sent to the V countdown block where the most appropriate window processing is performed to obtain V sync timing information which resets the counter. AKB and other V cycle timing are then generated from this reset timing. 2) H deflection signal processing The H pulse obtained through sync processing is phase-compared with the H deflection pulse input from Pin 44 to control the phase of the HDRIVE output and the horizontal position of the image projected on the CRT. In addition, the compensation signal generated from the V sawtooth wave is superimposed, and the vertical picture distortion is compensated. The H deflection pulse is used to H blanking of the video signal. When the pulse input from Pin 44 has a narrow width, the pulse generated by the IC can be added to the H deflection pulse and used as the H blanking pulse (HBLKSW). Pin 44 is normally pulse input, but if the pin voltage drops to the GND level, HDRIVE output stops and 1 is output to the status register (XRAY). To release this status, turn the power off and then on again. 3) V deflection signal processing The V sawtooth wave is generated at the cycle of the reset pulse output from the countdown system. After performing wide deflection processing for this sawtooth wave, picture distortion adjustment is performed by the VDRIVE and E/WDRIVE function circuits and the signal is output as the VDRIVE and E/WDRIVE signals. 4) Y signal processing Either CVIN, input from Pin 60, or YIN, output from Pin 62, is selected by the video switch and then is passed to the Y signal processing circuit as the Y signal. The input level is 1Vp-p. The Y signal passes through the subcontrast control, the trap for eliminating the chroma signal, the delay line, the sharpness control, the clamp and the black expansion circuits, and is then output to Pin 11 as YOUT. The differential waveform of the Y signal, advanced for about 200ns from YOUT is output from Pin 55 as the VM signal. The delay time is set by the bus register (DL). When CVIN is selected, the trap is on; when YIN is selected, the trap is off. The f0 of the internal filter is automatically adjusted within the IC. When the color killer function is operating, the f0 of the filter is not specified and rolling of display is generated. And, when status register COLOR SYS is not standard, turn the trap off. In addition, the f0 of the trap will be affected slightly by variations among IC, so fine adjustment through the I2C bus (TRAP-F0) may be required. - 40 -
CXA2050S
5) C signal processing The CVBS signal or chroma signal (specified input level: burst level of 300mVp-p) selected by the video switch passes through the ACC, TOT, chroma amplifier and demodulation circuits, becomes the R-Y and B-Y color difference signals, and is inverted for output on Pins 9 and 10. The color difference signals are averaged together by the external 1H delay line, and are input to Pins 14 and 15. Both color difference signals are clamped together with the Y signal input to Pin 13. They are then combined with the G-Y signal in the color control and axis control circuits. After Y/C mixing, the signals become the RGB signals. If the burst level goes to -37dB or less with respect to the specified input level, the color killer operates. In addition, the color system (PAL/NTSC) and the subcarrier frequency (4.43MHz/3.58MHz) are automatically identified according to the input chroma signal, and the internal VCO, demodulation circuit, axis control circuit, etc., are adjusted automatically. Furthermore, SECAM signals can also be identified if an external SECAM decoder is connected to Pin 7. In this case, Pins 9 and 10 and the SECAM decoder color difference output are linked together directly, and automatically one side goes to high impedance, the other goes to low impedance according to the input chroma signal, and then they are input to the external 1H delay line. System identification can be set to automatic or forced mode by the I2C bus (XTAL and COLOR SW). For identification result, the X'tal status selected as color system is output to the status registers (COLOR SYS and FSC). 6) RGB signal processing The RGB signals obtained from the Y/C block pass through the half-tone switch circuit (YM SW), the two switch circuits for the external RGB signals (YS1, YS2 SW), the picture control, dynamic color, gamma compensation, clamp, brightness control, drive adjustment, cut-off adjustment and auto cut-off circuits, and are output to Pins 28, 30 and 32. The RGB signals input to Pins 18, 19, 20, 23, 24, and 25 are 100 IRE, 100% white 0.7Vp-p signals, in accordance with the standard for normal video signals. If signals of 1.5Vp-p or more are input to Pins 23, 24, and 25, 78 IRE output is obtained (digital input). The voltage applied to Pin 34 (ABLIN) is compared with the internal reference voltage, integrated by the capacitor which is connected to Pin 35, and performs picture control and brightness control. In order to adjust the white balance (black balance), this IC has a drive control function which adjusts the gain between the RGB outputs and a cut-off control function which adjusts the DC level between the RGB outputs. Both drive control and cut-off control are adjusted by the I2C bus, with the Rch fixed and the G and Bch variable. An auto cut-off function (AKB) which forms a loop between the IC and CRT and performs adjustment automatically has also been added. This function can compensate for changes in the CRT with time. Auto cutoff operation is as follows. * R, G and B reference pulses for auto cut-off, shifted 1H each in the order mentioned, appear at the top of the picture (actually, in the overscan portion). The reference pulse uses 1H in the V blanking interval, and is output from each R, G and B output pin. * The cathode current (Ik) of each R, G and B output is converted to a voltage and input to Pin 33. * The voltage input to Pin 33 is compared with the reference voltage in the IC, and the current generated by the resulting error voltage charges the capacitors connected to Pins 27, 29 and 31 for the reference pulse interval and is held during all other interval. * The loop functions to change the DC level of the R, G and B outputs in accordance with the capacitor pin voltage so that the Pin 33 voltage matches the reference voltage in the IC. The Rch for the reference voltage in the IC is fixed and the G and Bch are cut-off controlled by the I2C bus. During G/B-CUTOFF center status, the loop functions so that the Rch for the reference pulse input to Pin 33 is 1Vp-p and the G and Bch are 0.81Vp-p. The reference pulse timing can be varied by the I2C bus. When AKB is not used, the IC can be set to manual cut-off mode with I2C bus settings. In this case, the DC level of the R, G and B outputs can be varied by applying voltages independently to Pins 27, 29 and 31. - 41 -
CXA2050S
4. Notes on operation Because the RGB signals and deflection signals output from the CXA2050S are DC direct connected, the board pattern must be designed consideration given to minimizing interference from around the power supply and GND. Do not separate the GND patterns for each pin; a solid earth is ideal. Design power supply as low impedance as possible. when impedance of power supply is high, video block power supply VCC interferes with deflection block power supply DVCC, and its deflection operation may be unstable. For this countermeasure, inputting LC to each SVCC and DVCC stabilizes the operation because power supply's interference is reduced. Locate the power supply side of the by-pass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also, locate the XTAL oscillator, ceramic oscillator and IREF resistor as near to the pin as possible, and do not wire signal lines near this pin. Drive the Y, external Y/color difference and external RGB signals at a sufficiently low impedance, as these signals are clamped when they are input using the capacitor connected to the input pin. DC bias is applied to the chroma signal within the IC. Input the chroma signal with low impedance via an external capacitor. Use a resistor (such as a metal film resistor) with an error of less than 1% for the IREF pin. Use a capacitor, such as an MPS (metalized polyester capacitor) with a small tan for SAWOSC. When using a line frequency FH of 15625Hz for the main clock (PAL-B, G, etc.), Murata's Ceralock CSB500F63 is recommended. This will yield a free-running frequency in the neighborhood of 15625Hz.
- 42 -
CXA2050S
Curve Data I2C bus data conforms to the "I2C Bus Register Initial Settings" of the Electrical Characteristics Measurement Conditions (P. 22).
V-SIZE
4.0 3.6 3.4 3.5 3.2
V-POSITION
V [V]
V [V]
3.0
3.0
2.8 2.5 V-SIZE = 0 V-SIZE = 1F V-SIZE = 3F 2.0 0 5 10 Time [ms] 15 20 2.6 V-POSITION = 0 V-POSITION = 1F V-POSITION = 3F 0 5 10 Time [ms] 15 20
2.4
S-CORR
3.6 3.4 3.6 3.4
V-LIN
3.2
3.2
V [V]
3.0
V [V]
3.0
2.8 S-CORR = 0 S-CORR = 7 S-CORR = F
2.8 V-LIN = 0 V-LIN = 7 V-LIN = F
2.6
2.6
2.4 0 5 10 Time [ms] 15 20
2.4 0 5 10 Time [ms] 15 20
V-ASPECT
3.8 3.6 3.4 3.2 3.8 3.6 3.4 3.2
V-SCROLL
V [V]
3.0 2.8 2.6 2.4 2.2 0 5 10 Time [ms] 15 20 V-ASPECT = 0 V-ASPECT = 1F V-ASPECT = 3F
V [V]
3.0 2.8 2.6 2.4 2.2 0 5 10 Time [ms] 15 20 V-SCROLL = 0 V-SCROLL = 1F V-SCROLL = 3F
- 43 -
CXA2050S
UP-VLIN
3.6 3.4 3.6 3.4
LO-VLIN
3.2
3.2
V [V]
V [V]
3.0
3.0
2.8 UP-VLIN = 0 UP-VLIN = 7 UP-VLIN = F
2.8 LO-VLIN = 0 LO-VLIN = 7 LO-VLIN = F
2.6
2.6
2.4 0 5 10 Time [ms] 15 20
2.4 0 5 10 Time [ms] 15 20
PIN-COMP
4.2 4.0 3.8 3.6 4.2 4.0 3.8 3.6
PIN-PHASE
V [V]
V [V]
PIN-COMP = 0 PIN-COMP = 1F PIN-COMP = 3F 0 5 10 Time [ms] 15 20
3.4 3.2
3.4 3.2 3.0 2.8
3.0 2.8 2.6 PIN-PHASE = 0 PIN-PHASE = 7 PIN-PHASE = F 0 5 10 Time [ms] 15 20
UP-CPIN
4.0 4.0
LO-CPIN
3.6
3.6
V [V]
V [V]
3.2
3.2
2.8 UP-CPIN = 0 UP-CPIN = 7 UP-CPIN = F 5 10 Time [ms] 15 20
2.8 LO-CPIN = 0 LO-CPIN = 7 LO-CPIN = F 0 5 10 Time [ms] 15 20
2.4 0
2.4
- 44 -
CXA2050S
H-SIZE
4.8 3.5
H-POSITION
4.4
3
Time [s]
4.0
2.5
V [V]
3.6
2
53 HSIN
SYNC center t [sec]
3.2
H-SIZE = 0 H-SIZE = 1F H-SIZE = 3F 0 5 10 Time [ms] 15 20
1.5
44 AFCPIN
6sec 12sec
1
0
2
4
6
8 DATA
10
12
14
TRAP OFF
5 0 -5 -10 800
DELAY
CVIN - YOUT delay time [ns]
700 600
Gain [dB]
-15 -20 -25 -30 -35 0 1 2 3 4 5 6 Frequency [MHz] 3.58MHz TRAP OFF = 0 4.43MHz TRAP OFF = 0 TRAP OFF = 1
500 400
300
200
0
1
2
3
4 DATA
5
6
7
SHARPNESS (SHP F0 = 0)
6 4 2 SHARPNESS = 0 SHARPNESS = 7 SHARPNESS = F 6 4 2
SHARPNESS (SHP F0 = 1)
SHARPNESS = 0 SHARPNESS = 7 SHARPNESS = F
Gain [dB]
Gain [dB]
0 -2 -4 -6 1 2 3 4 5 6 7 8 9 10
0 -2 -4 -6 1 2 3 4 5 6 7 8 9 10
Frequency [MHz]
Frequency [MHz]
- 45 -
CXA2050S
PICTURE
0 3 2 -4 1
SUB-CONT
Gain [dB]
-8
Gain [dB]
0 -1 -2 -3
-12
-14
0
10
20
30 DATA
40
50
60
-4
0
2
4
6
8 DATA
10
12
14
COLOR
10 5 0 3 2 1
SUB-COLOR
Gain [dB]
COLOR OFF when DATA = 0 (-40dB or less)
Gain [dB]
-5 -10 -15 -20 -25 0 10 20 30 DATA 40 50 60
0 -1 -2 -3 -4 0 2 4 6 8 DATA 10 12 14
Potential difference between Rch reference pulse level and black level [Vp-p]
Potential difference between Rch reference pulse level and black level [Vp-p]
BRIGHT
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 0 10 20 30 DATA SUB-BRIGHT = 0 SUB-BRIGHT = 1F SUB-BRIGHT = 3F 40 50 60
SUB-BRIGHT
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0 10 20 30 DATA 40 50 60
- 46 -
CXA2050S
B-DRIVE, G-DRIVE
2 4.5 4.0 0 3.5
GAMMA
Rch output [V]
Gain [dB]
3.0 2.5 2.0 1.5 GAMMA = 0 GAMMA = 1 GAMMA = 2 GAMMA = 3 0 20 40 60 80 100
-2
-4
-6 0 10 20 30 40 50 60 70 DATA
1.0 CVIN input amplitude [IRE]
G-CUTOFF, B-CUTOFF
4.1 3.9 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0
AKB open loop characteristics
IKIN reference pulse voltage [V]
3.7 3.5 3.3 3.1 2.9 2.7 2.5 0 2 4 6 8 DATA 10 12 14 16 Gch, Bch IK clamp level Rch
V [V]
Reference pulse voltage (AKBOFF = 0) RGBOUT black level voltage (AKBOFF = 0, 1) 3.5 4.0 4.5 5.0 5.5 6.0
Voltage applied R, G and B sample-and-hold capacitance pins [V]
- 47 -
CXA2050S
Package Outline
Unit: mm
64PIN SDIP (PLASTIC)
57.6
19.05 0.2
1.778
0.5 MIN
4.0 0.25
0.45 0.2 1.0 0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-051 SDIP064-P-0750 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER ALLOY 9.0g
- 48 -
2.54 MIN
17.0 0.4
0 to 15
59.0MAX
- 0.11 5 5 + 0.0 0.2

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